1. Field of the Invention
The present invention relates to a signal input/output circuit for semiconductor integrated circuit, particularly to a signal input/output circuit for a semiconductor integrated circuit capable of preventing the semiconductor integrated circuit from generating an internal signal generated from the semiconductor integrated circuit itself when an output transistor thereof is destroyed or when a signal input/output terminal is short-circuited with a voltage source which negates signal output of the semiconductor integrated circuit.
2. Description of the Related Art
FIG. 1 is a circuit diagram showing a construction example of a reset, signal input/output circuit, as an example of a conventional signal input/output circuit for a semiconductor integrated circuit.
In FIG. 1, reference numeral 10 designates a semiconductor integrated circuit which is provided with a reset signal input/output terminal 1. The reset signal input/output terminal 1 is pulled up by a resistance 11 having a proper resistance value at the outside of the semiconductor integrated circuit 10.
At the inside of the semiconductor integrated circuit 10, there are provided an N-channel transistor 2 whose drain is connected to the reset signal input/output terminal 1, and a reset input circuit 3 being composed, for example, of a schmitt trigger gate, whose negative logic input end is connected to the reset signal input/output terminal 1 through a protection resistance 4.
A source of the N-channel transistor 2 is connected to the ground voltage source of the semiconductor integrated circuit 10, and a gate of the same is connected to a signal line 5.
The signal line 5 is the one for receiving an internal reset requesting signal TWD whose active level is "H" and which is generated from a circuit (not shown) inside of the semiconductor integrated circuit 10 when semiconductor integrated circuit 10 judges that it is necessary to be reset itself, to the gate of the N-channel transistor 2.
Accordingly, since the N-channel transistor 2 is on when the "H" level internal reset requesting signal TWD is given to the N-channel transistor 2 through the signal line 5, the reset signal input/output terminal 1 is connected to the ground voltage source and becomes "L" level. At the same time, since a negative logic input end of the reset input circuit 3 for resetting the semiconductor integrated circuit 10 also becomes "L" level, the reset signal RST which is the output signal of the reset input circuit 3 becomes active level ("H" level). That is, the signal line 5 is also a reset requesting signal line of the semiconductor integrated circuit 10 itself.
Next, explanation will be given on the operation of a conventional reset signal input/output circuit shown in FIG. 1.
Usually, to the reset signal input/output terminal 1, an external reset requesting signal #REQ of nonactive level (in this case, "H" level) is inputted, and internal reset requesting signal TWD is "L" level. In this usual state, since the N-channel transistor 2 is off, the external reset requesting signal #REQ of "H" level is inputted to the negative logic input end of the reset input circuit 3 from the reset signal input/output terminal 1. Accordingly, the reset input circuit 3 outputs the reset signal RST of "L" level obtained by inverting input level to the negative logic input end thereof.
When it is necessary to reset the semiconductor integrated circuit 10 from the outside, active level signal, in this case, the external reset requesting signal #REQ of "L" level is inputted to the reset signal input/output terminal 1. Thereby, since "L" level signal is input ted to the negative logic input end of the reset input circuit 3, the reset input circuit 3 inverts the inputted level and outputs the reset signal RST of active level ("H" level) into the semiconductor integrated circuit 10.
On the other hand, when the semiconductor integrated circuit 10 itself judges or determines that it is necessary to be reset, the internal reset requesting signal TWD of "H" level is generated by a circuit (not shown) inside of the semiconductor integrated circuit 10. The internal reset requesting signal TWD of "H" level is given or transmitted to the gate of the N-channel transistor 2 through the signal line 5, thereby the N-channel transistor 2 is on to connect the reset signal input/output terminal 1 with the ground voltage source, therefore the reset signal input/output terminal 1 becomes "L" level. Accordingly, from the outside of the semiconductor integrated circuit 10, it becomes possible to know the generation or state (to become "H" level) of the internal reset requesting signal TWD by the fact that the reset signal input/output terminal 1 becomes "L" level. At the same time, since "L" level signal is inputted to the negative logic input end of the reset input circuit 3 connected to the reset signal input/output terminal 1, the reset input circuit 3 inverts the inputted level and outputs the reset signal RST of active level ("H" level).
In the aforementioned reset signal input/output circuit as a conventional signal input/output circuit for a semiconductor integrated circuit shown in FIG. 1, when the reset signal input/output terminal, for example, is connected with polarity which does not generate reset, "H" level potential, to be concrete, in low impedance, since level of the reset signal input/output terminal is voltage divided even when the semiconductor integrated circuit itself generates internal reset requesting signal, the level does not become "L" level, and the semiconductor integrated circuit is not reset.
Even when N-channel transistor is destroyed due to static electricity or the like and signal of "L" level can't be outputted, potential of reset signal input/output terminal does not become "L" level, therefore resetting of the semiconductor integrated circuit itself is not carried out.
When the circuit falls into such a state, there is a possibility that is enters running state, since not only reset requesting signal to the outside can't be outputted but also the semiconductor integrated circuit itself is not reset.